Q:Is the SPI interface used?

A: Connect COMM_SEL (pad 20) to GND.
A: SPI is LVCMOS 1.8V compatible.

Q:Is the UART output high logic level voltage VCC tolerant?

A: Connect VIO_EXT (pad 3) to VCC (pad 8).
A: UART voltage level is externally defined by VIO_EXT pad.

Q:Is the UART interface used?

A: Leave COMM_SEL (pad 20) floating.
A: Connect series ceramic resistor of 22-49Ω and shunt ceramic capacitor of 12-22pF to form low pass filter on GPS TX (pad 2) and GPS RX (pad 1) lines.

Q:Does the power source capable to handle current consumption requirements?

A: Maximum current consumption during acquisition is 35mA.
A: Inrush current during module power up may exceed 120mA.

Q:Is the power source ripple not exceeding maximum allowed?

A: Voltage ripple below 300mVp-p allowed for frequency under 10KHz.
A: Voltage ripple below 30mVp-p allowed for frequency between 10KHz and 100KHz.
A: Voltage ripple below 10mVp-p allowed for frequency between 100KHz and 1MHz.
A: Voltage ripple below 3mVp-p allowed for frequency above 1MHz.

Q:Is the main power supply voltage (VCC) within the specified range?

A:Verify 3.3V to 5.5V. Raw battery voltage source is accepted.
i The module will shut down when voltage trip below 3.25V.
i nRESET pad will be internally held in low state.
Q:Single supply operation required?
A:Connect VIO_EXT to VCC.

Q:Is the UART buffers power supply voltage (VIO_EXT) within the specified range?

A: Verify VIO_EXT from 1.8V to VCC.
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